In this paper, an N-type silicon line tunneling TFET (LT-TFET) with an ultra-shallow N⁺ pocket was proposed. The pocket was formed by using the germanium preamorphization implantation (Ge PAI), arsenic ultra-low energy implantation and spike annealing. Due to the Ge PAI, the tunneling probability was improved significantly. As a result, a high on-state current of $40 \mu \text{A}/\mu \text{m}$ , a minimum subthreshold swing (SS) of 69 mV/decade and an average SS of 80 mV/decade over 5 decades of drain current were achieved with $\text{V}_{\mathrm{ DS}} =\,\,\text{V}_{\mathrm{ GS}}=1$ V at room temperature. It is shown that once the trap assisted tunneling is suppressedat the low temperature, the band-to-band tunneling becomes dominant. When the temperature decreases from 300 K to 4.9 K, the on-state current only reduces 20% and a minimumpoint SS of 10 mV/decadewas obtained. The LT-TFET exhibits improved transconductance efficiency at deep cryogenic temperature range. The proposed structure in this work shows attractive merits in the cryogenic digital and analog application.

中文翻译：

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具有高驱动电流的新型硅线隧道 TFET 的制造和表征

在本文中，提出了一种具有超浅 N ⁺口袋的 N 型硅线隧穿 TFET (LT-TFET) 。口袋是通过使用锗预非晶化注入（Ge PAI）、砷超低能量注入和尖峰退火形成的。由于Ge PAI，隧穿概率显着提高。因此，高导通电流为 $40 \mu \text{A}/\mu \text{m}$ ，在 5 个十倍频程的漏极电流中，最小亚阈值摆幅 (SS) 为 69 mV/十倍频程，平均 SS 为 80 mV/十倍频程 $\text{V}_{\mathrm{ DS}} =\,\,\text{V}_{\mathrm{ GS}}=1$ V 在室温下。结果表明，一旦陷阱辅助隧穿在低温下被抑制，带间隧穿将成为主导。当温度从 300 K 降低到 4.9 K 时，导通电流仅降低 20%，获得了 10 mV/decade 的最小点 SS。LT-TFET 在深低温范围内表现出改进的跨导效率。这项工作中提出的结构在低温数字和模拟应用中显示出有吸引力的优点。