In this paper, the design of frequency-locked loop (FLL) is proposed based on computationally efficient discrete Fourier transform (DFT) structures. In recent years, the DFT structures are evolved as sliding DFT (SDFT), modulated SDFT, hopping DFT (HDFT), modulated HDFT, and sliding-windowed infinite Fourier transform. Considering their tuned filter characteristics, an attempt has been made to obtain a solution for the instantaneous frequency estimation problem of the input signal under varying center frequency condition. In each DFT structure, the $k$ th bin in-phase and quadrature components are separated for instantaneous signal extraction. The feedback loop is designed around these DFT structures, and it was observed that the frequency responses exhibit flat magnitude and phase interestingly when compared with the open-loop structures. Hence, an adaptive sampling frequency adjustment scheme is proposed for these structures as FLL to estimate the instantaneous frequency of the input signal for the wide variation in center frequency. These FLLs with different DFT structures are tested for dynamic performance and wide operating range. The proposed FLLs are implemented in field-programmable gate array (FPGA), and the experimental investigations have been carried out for frequency estimation. Further experimental investigations on these FLLs as a system on chip were carried out with area and power analysis.

中文翻译：

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用于频率估计的计算高效离散傅立叶变换的综合性能评估

在本文中，基于计算效率高的离散傅立叶变换 (DFT) 结构提出了锁频环 (FLL) 的设计。近年来，DFT结构演变为滑动DFT（SDFT）、调制SDFT、跳跃DFT（HDFT）、调制HDFT和滑动窗口无限傅里叶变换。考虑到它们的调谐滤波器特性，已经尝试获得变化中心频率条件下输入信号的瞬时频率估计问题的解决方案。在每个 DFT 结构中，第 k 个 bin 的同相和正交分量被分离以进行瞬时信号提取。反馈回路是围绕这些 DFT 结构设计的，与开环结构相比，观察到频率响应表现出平坦的幅度和相位，这很有趣。因此，针对这些结构提出了一种自适应采样频率调整方案，如 FLL，以估计输入信号的瞬时频率以适应中心频率的广泛变化。这些具有不同 DFT 结构的 FLL 都经过动态性能和宽工作范围的测试。所提出的 FLL 在现场可编程门阵列 (FPGA) 中实现，并且已经进行了频率估计的实验研究。使用面积和功率分析对这些 FLL 作为片上系统进行了进一步的实验研究。这些具有不同 DFT 结构的 FLL 都经过动态性能和宽工作范围的测试。所提出的 FLL 是在现场可编程门阵列 (FPGA) 中实现的，并且已经进行了频率估计的实验研究。使用面积和功率分析对这些 FLL 作为片上系统进行了进一步的实验研究。这些具有不同 DFT 结构的 FLL 都经过动态性能和宽工作范围的测试。所提出的 FLL 在现场可编程门阵列 (FPGA) 中实现，并且已经进行了频率估计的实验研究。使用面积和功率分析对这些 FLL 作为片上系统进行了进一步的实验研究。