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Bringing the SEED Approach to the Next Level: Generating IC Models for System ESD and Electrical Stress Simulation out of Design Data
IEEE Transactions on Electromagnetic Compatibility ( IF 2.1 ) Pub Date : 2020-02-01 , DOI: 10.1109/temc.2018.2888691
Michael Ammer , Yiqun Cao , Andreas Rupp , Martin Sauter , Linus Maurer

System-level electrostatic discharge (ESD) robustness design according to ISO10605 or IEC 61000-4-2 on printed circuit board (PCB) level is still a challenge). The blocking point is often the lack of accurate models of complete integrated circuits (ICs). Previously published methodologies to generate ESD models for ICs are all based on measurements of the complete IC, showing the drawback of complex, difficult and time-consuming measurements. This paper proposes a novel methodology to generate ESD models for complete ICs out of their design data. The proposed approach requires no measurements with the complete IC and hence can reduce the effort significantly. Furthermore, the methodology offers the possibility for automation, which further reduces the number of needed resources. It is based on the approach of black box modeling. This means simplified behavioral models are used, which contain solely the characteristic behavior in case of disturbance pulses. The methodology focuses on the transient behavior as well as the physical destruction limits of smart power products. Behavioral model in this context means the transient response due to disturbance pulse in terms of voltage drops and current drain. The procedure is explained and verified step by step on an exemplary product. It can be easily transferred to other products. System designers receive a powerful model for targeting certain robustness of their system against transient disturbances. Further enhancements of the methodology can enable also the soft failure assessment by simulation.

中文翻译:

将 SEED 方法提升到新的水平:从设计数据中生成用于系统 ESD 和电气应力仿真的 IC 模型

根据 ISO10605 或 IEC 61000-4-2 在印刷电路板 (PCB) 级别进行的系统级静电放电 (ESD) 鲁棒性设计仍然是一个挑战。阻塞点通常是缺乏完整集成电路 (IC) 的准确模型。之前发布的为 IC 生成 ESD 模型的方法都是基于对整个 IC 的测量,显示出测量复杂、困难和耗时的缺点。本文提出了一种新方法,可根据设计数据为完整 IC 生成 ESD 模型。所提出的方法不需要对完整的 IC 进行测量,因此可以显着减少工作量。此外,该方法提供了自动化的可能性,这进一步减少了所需资源的数量。它基于黑盒建模的方法。这意味着使用简化的行为模型,其中仅包含干扰脉冲情况下的特征行为。该方法侧重于智能电源产品的瞬态行为以及物理破坏极限。在这种情况下,行为模型是指由于电压降和电流消耗方面的干扰脉冲引起的瞬态响应。在示例产品上逐步解释和验证该过程。它可以很容易地转移到其他产品上。系统设计人员收到了一个强大的模型,用于针对瞬态干扰确定其系统的某些鲁棒性。该方法的进一步增强还可以通过模拟进行软故障评估。该方法侧重于智能电源产品的瞬态行为以及物理破坏极限。在这种情况下,行为模型是指由于电压降和电流消耗方面的干扰脉冲引起的瞬态响应。在示例产品上逐步解释和验证该过程。它可以很容易地转移到其他产品上。系统设计人员收到了一个强大的模型,用于针对瞬态干扰确定其系统的某些鲁棒性。该方法的进一步增强还可以通过模拟进行软故障评估。该方法侧重于智能电源产品的瞬态行为以及物理破坏极限。在这种情况下,行为模型是指由于电压降和电流消耗方面的干扰脉冲引起的瞬态响应。在示例产品上逐步解释和验证该过程。它可以很容易地转移到其他产品上。系统设计人员收到了一个强大的模型,用于针对瞬态干扰确定其系统的某些鲁棒性。该方法的进一步增强还可以通过模拟进行软故障评估。在示例产品上逐步解释和验证该过程。它可以很容易地转移到其他产品上。系统设计人员收到了一个强大的模型,用于针对瞬态干扰确定其系统的某些鲁棒性。该方法的进一步增强还可以通过模拟进行软故障评估。在示例产品上逐步解释和验证该过程。它可以很容易地转移到其他产品上。系统设计人员收到了一个强大的模型,用于针对瞬态干扰确定其系统的某些稳健性。该方法的进一步增强还可以通过模拟进行软故障评估。
更新日期:2020-02-01
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