Since nondeterministic behavior is key to exposing shared-memory errors, nonsynchronized parallel programs are often used for verification and test of multicore chips. In the verification phase, however, the slow execution in a simulator requires nonconventional constraints for enabling error exposure with shorter programs. This paper proposes two novel techniques that build upon conventional random test generation for efficient shared-memory verification. The first technique exploits canonical dependence chains for constraining the random generation of instruction sequences so that the races induced at runtime are likely to raise the coverage of state transitions due to memory events conflicting at a same shared location. The second one exploits address space constraints for biasing random address assignment so that the competition of distinct shared locations for a same cache set can be controlled for raising the coverage of state transitions due to eviction events. We built generators relying on each of the proposed techniques, as well as on their combination, and we compared them to a conventional constrained random test generator for 8, 16, and 32-core architectures. Each of the four generators synthesized 1200 distinct test programs for verifying ten faulty designs derived from each of the three architectures (144 000 verification runs in total). For 32-core designs, the combination of the proposed techniques made at least 50% of the generation space capable of exposing errors, improved the median functional coverage by 44% and 83% at the two highest hierarchical levels, and reduced the average verification effort by one order of magnitude in many cases.

中文翻译：

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链接和偏置：共享内存验证的测试生成技术

由于不确定性行为是暴露共享内存错误的关键，因此非同步并行程序通常用于验证和测试多核芯片。然而，在验证阶段，模拟器中的缓慢执行需要非常规的约束，以便通过较短的程序实现错误暴露。本文提出了两种建立在传统随机测试生成基础上的新技术，以实现高效的共享内存验证。第一种技术利用规范依赖链来约束指令序列的随机生成，以便由于在同一共享位置发生冲突的内存事件，在运行时引发的竞争可能会提高状态转换的覆盖率。第二个利用地址空间约束来偏置随机地址分配，以便可以控制相同缓存集的不同共享位置的竞争，以提高由于驱逐事件引起的状态转换的覆盖率。我们构建了依赖于所提出的每种技术及其组合的生成器，并将它们与用于 8、16 和 32 核架构的传统约束随机测试生成器进行了比较。四个生成器中的每一个都合成了 1200 个不同的测试程序，用于验证源自三种架构中每一个的十个错误设计（总共 144 000 次验证运行）。对于 32 核设计，所提出技术的组合使至少 50% 的生成空间能够暴露错误，