Abstract Fast Internet Protocol Version 4 (IPv4) lookup is one of the key challenges that have always been faced with growing internet speed. Next generation networks promise hundreds of gigabit communication bandwidths. To support such high data rates, core networking devices require very fast IPv4 lookup for incoming packets to sustain their functionality. Researchers from academia and industry have contributed widely towards this problem, presenting numerous techniques and algorithms to improve lookup times. In this paper, a bit vector-based IP lookup engine is presented that implements parallel units to achieve 4.3 Billion Packets Per Second (BPPS) lookup speeds for 5 fields. Implementations are done using dual port Distributed RAM (DRAM) on state-of-the-art Xilinx Virtex 7 series Field Programmable Gate Arrays (FPGA). Post place and route results for different configurations showed that the proposed design consumes much less memory, facilitating multiple engines on a single chip whilst maintaining a very low overall power profile.

中文翻译：

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下一代网络的数十亿数据包查找

摘要 快速 Internet 协议版本 4 (IPv4) 查找是互联网速度不断提高所面临的主要挑战之一。下一代网络承诺提供数百千兆位的通信带宽。为了支持如此高的数据速率，核心网络设备需要非常快速的 IPv4 查找传入数据包以维持其功能。学术界和工业界的研究人员为解决这个问题做出了广泛贡献，提出了许多技术和算法来改善查找时间。在本文中，提出了一种基于位向量的 IP 查找引擎，该引擎实现了并行单元，以实现 5 个字段的每秒 43 亿包 (BPPS) 查找速度。在最先进的 Xilinx Virtex 7 系列现场可编程门阵列 (FPGA) 上使用双端口分布式 RAM (DRAM) 完成实施。