Spread-spectrum clocking (SSC) is an active solution to attenuate electromagnetic interference (EMI) in Gb/s serial communication systems by slightly modulating the phase-locked loop (PLL) output clock frequency. This article presents a phase-compensated spread-spectrum clock generator (SSCG) with the state-of-the-art EMI reduction and clock rms jitter performance. A 32-slice scaled resistor-based buffer is proposed to realize the phase interpolator (PI). The proposed design has no static current and low complexity without active device matching requirement. The 32-slice PI structure can achieve a simulated 22-dB EMI reduction with a 32-step triangular modulation profile. The proposed SSCG chip with a charge-pump-based fractional- $N$ radio frequency (RF)-PLL and a source-series-terminated (SST) driver is fabricated using a 55-nm CMOS process. Measurement result shows that EMI reduction of the 5-GHz output clock power spectrum is 19.44 dB under 0.5% down-spread. The rms jitters with SSC-off and SSC-on, adopting a second-order clock recovery in oscilloscope, are 630 and 640 fs, respectively. The normalized power consumption is 9.3 mW/GHz, and the core area occupation is 0.092 mm2.

中文翻译：

---

具有 19.44dB EMI 降低和 10fs 额外 RMS 抖动的 32 步相位补偿扩频 RF-PLL

扩频时钟 (SSC) 是一种主动解决方案，可通过轻微调制锁相环 (PLL) 输出时钟频率来衰减 Gb/s 串行通信系统中的电磁干扰 (EMI)。本文介绍了一种具有最先进的 EMI 降低和时钟均方根抖动性能的相位补偿扩频时钟发生器 (SSCG)。提出了一个 32 片缩放的基于电阻器的缓冲器来实现相位内插器 (PI)。所提出的设计没有静态电流和低复杂度，没有有源器件匹配要求。32 片 PI 结构可以通过 32 步三角调制分布实现模拟的 22dB EMI 降低。所提议的 SSCG 芯片具有基于电荷泵的分数 N$ 射频 (RF)-PLL 和源串联端接 (SST) 驱动器，是使用 55 纳米 CMOS 工艺制造的。测量结果表明，在 0.5% 向下扩展下，5 GHz 输出时钟功率谱的 EMI 降低为 19.44 dB。SSC-off 和 SSC-on 的 rms 抖动，采用示波器中的二阶时钟恢复，分别为 630 和 640 fs。归一化功耗为9.3 mW/GHz，核心面积占用为0.092 mm2。