In the past few years, thin-film transistor (TFT) technology has experienced a rapid transition from amorphous silicon- (a-Si:H) and polysilicon-based TFTs to zinc oxide (ZnO)-based TFTs, and because of this transition, transparent TFTs have become a reality. In ZnO TFTs, which operate in accumulation mode, the threshold voltage has remained ambiguous due to the existence of grain boundary traps in the polycrystalline semiconducting channel. This paper provides an analytical relationship of threshold voltage with grain boundary trap density by assuming the grain boundary is a continuous one-dimensional line charge. A high density of grain boundary traps leads to a high threshold voltage. However, its effect can be minimized by employing a high-κ gate dielectric. In this work, we have demonstrated the reduction of threshold voltage in a ZnO TFT by using ZrO₂ as a gate dielectric. A study of a ZnO/ZrO₂ interface is reported by fabricating a metal–insulator–semiconductor capacitor structure. This interface is studied using capacitance–voltage (C–V) and current–voltage (I–V) characteristics. The ZnO TFT with a ZrO₂ gate dielectric exhibits a low subthreshold slope (131 mV decade⁻¹), low gate leakage current density (2.94 × 10⁻⁷ A cm⁻²) and low threshold voltage (1.2 V). However, it also exhibits a counterclockwise hysteresis of −1.4 V, which is attributed to the existence of oxygen vacancies.

在过去的几年中，薄膜晶体管（TFT）技术经历了从非晶硅（a-Si：H）和基于多晶硅的TFT到基于氧化锌（ZnO）的TFT的快速转变，透明TFT已成为现实。在以累积模式工作的ZnO TFT中，由于在多晶半导体沟道中存在晶界陷阱，因此阈值电压一直不明确。本文通过假设晶界是连续的一维线电荷来提供阈值电压与晶界陷阱密度的解析关系。晶界陷阱的高密度导致高阈值电压。但是，通过采用高κ栅极电介质。在这项工作中，我们已经证明了通过使用ZrO ₂作为栅极电介质来降低ZnO TFT中的阈值电压。ZnO / ZrO ₂界面的研究是通过制造金属-绝缘体-半导体电容器结构来进行的。使用电容电压（C – V）和电流电压（I – V）特性研究此接口。具有ZrO ₂栅极电介质的ZnO TFT表现出较低的亚阈值斜率（131 mV十进制^-1），较低的栅极泄漏电流密度（2.94×10 ^-7  A cm ^-2））和低阈值电压（1.2 V）。但是，它也表现出-1.4 V的逆时针磁滞，这归因于氧空位的存在。