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Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis
arXiv - CS - Hardware Architecture Pub Date : 2020-03-29 , DOI: arxiv-2003.13054
Maria A. D\'avila-Guzm\'an and Rub\'en Gran Tejero and Mar\'ia Villarroya-Gaud\'o and Dar\'io Su\'arez Gracia

The increasing demand of dedicated accelerators to improve energy efficiency and performance has highlighted FPGAs as a promising option to deliver both. However, programming FPGAs in hardware description languages requires long time and effort to achieve optimal results, which discourages many programmers from adopting this technology. High Level Synthesis tools improve the accessibility to FPGAs, but the optimization process is still time expensive due to the large compilation time, between minutes and days, required to generate a single bitstream. Whereas placing and routing take most of this time, the RTL pipeline and memory organization are known in seconds. This early information about the organization of the upcoming bitstream is enough to provide an accurate and fast performance model. This paper presents a performance analytical model for HLS designs focused on memory bound applications. With a careful analysis of the generated memory architecture and DRAM organization, the model predicts the execution time with a maximum error of 9.2% for a set of representative applications. Compared with previous works, our predictions reduce on average at least $2\times$ the estimation error.

中文翻译:

使用高级综合编译的内存受限应用程序的分析模型

对提高能效和性能的专用加速器的需求不断增长,这凸显了 FPGA 是实现两者的有前途的选择。然而,用硬件描述语言对 FPGA 进行编程需要花费大量时间和精力才能达到最佳效果,这阻碍了许多程序员采用这种技术。高级综合工具提高了对 FPGA 的可访问性,但由于生成单个比特流所需的编译时间很长,从几分钟到几天不等,因此优化过程仍然很耗时。虽然布局和布线需要花费大部分时间,但 RTL 管道和内存组织在几秒钟内就知道了。有关即将到来的比特流组织的早期信息足以提供准确且快速的性能模型。本文提出了一个针对 HLS 设计的性能分析模型,重点是内存绑定应用程序。通过对生成的内存架构和 DRAM 组织的仔细分析,该模型预测了一组具有代表性的应用程序的执行时间,最大误差为 9.2%。与之前的工作相比,我们的预测平均减少了至少 $2\times$ 的估计误差。
更新日期:2020-03-31
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