In the context of growing the adoption of advanced sensors and systems for active vehicle safety and driver assistance, an increasingly important issue is the security of the information exchanged between the different sub-systems of the vehicle. Random number generation is crucial in modern encryption and security applications as it is a critical task from the point of view of the robustness of the security chain. Random numbers are in fact used to generate the encryption keys to be used for ciphers. Consequently, any weakness in the key generation process can potentially leak information that can be used to breach even the strongest cipher. This paper presents the architecture of a high performance Random Number Generator (RNG) IP-core, in particular a Cryptographically Secure Pseudo-Random Number Generator (CSPRNG) IP-core, a digital hardware accelerator for random numbers generation which can be employed for cryptographically secure applications. The specifications used to develop the proposed project were derived from dedicated literature and standards. Subsequently, specific architecture optimizations were studied to achieve better timing performance and very high throughput values. The IP-core has been validated thanks to the official NIST Statistical Test Suite, in order to evaluate the degree of randomness of the numbers generated in output. Finally the CSPRNG IP-core has been characterized on relevant Field Programmable Gate Array (FPGA) and ASIC standard-cell technologies.

中文翻译：

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基于SHA2算法的密码安全伪随机数生成器IP核。

在越来越多地采用先进的传感器和系统来实现主动车辆安全和驾驶员辅助的背景下，一个日益重要的问题是车辆不同子系统之间交换信息的安全性。随机数生成在现代加密和安全应用中至关重要，因为从安全链的健壮性角度来看，随机数生成是一项至关重要的任务。实际上，随机数用于生成要用于密码的加密密钥。因此，密钥生成过程中的任何弱点都可能潜在地泄漏信息，这些信息甚至可以用来破解最强的密码。本文介绍了高性能随机数生成器（RNG）IP核的体系结构，尤其是加密安全的伪随机数生成器（CSPRNG）IP核，用于随机数生成的数字硬件加速器，可用于密码安全应用程序。用于开发拟议项目的规范源自专门的文献和标准。随后，研究了特定的体系结构优化，以实现更好的定时性能和非常高的吞吐量值。感谢官方的NIST统计测试套件对IP核进行了验证，以便评估输出中生成的数字的随机程度。最后，CSPRNG IP核已通过相关的现场可编程门阵列（FPGA）和ASIC标准单元技术进行了表征。用于开发拟议项目的规范源自专门的文献和标准。随后，研究了特定的体系结构优化，以实现更好的定时性能和非常高的吞吐量值。感谢官方的NIST统计测试套件对IP核进行了验证，以便评估输出中生成的数字的随机程度。最后，CSPRNG IP核已通过相关的现场可编程门阵列（FPGA）和ASIC标准单元技术进行了表征。用于开发拟议项目的规范源自专门的文献和标准。随后，研究了特定的体系结构优化，以实现更好的定时性能和非常高的吞吐量值。感谢官方的NIST统计测试套件对IP核进行了验证，以便评估输出中生成的数字的随机程度。最后，CSPRNG IP核已通过相关的现场可编程门阵列（FPGA）和ASIC标准单元技术进行了表征。为了评估输出中生成的数字的随机性。最后，CSPRNG IP核已通过相关的现场可编程门阵列（FPGA）和ASIC标准单元技术进行了表征。为了评估输出中生成的数字的随机性。最后，CSPRNG IP核已通过相关的现场可编程门阵列（FPGA）和ASIC标准单元技术进行了表征。