We present a dual-chiplet interposer-based system-in-package (SiP) octo-core processor using Chip-on-Wafer-on-Substrate (CoWoS) technology. Each of the two identical chiplets is implemented in 7-nm CMOS with 15 metal layers and has four Arm Cortex-A72 processor cores operating at 4.0 GHz. A bidirectional mesh bus with 2-mm flop-to-flop distance is distributed throughout the chiplet for high-speed on-die data transport above 4.0 GHz. The chiplets communicate with each other through ultrashort reach (0.5 mm long) interposer channels using a Low-voltage-In-Package-INterCONnect (LIPINCON) clock-forwarded parallel interface. The scalable link module offers 320 GB/s of aggregate bandwidth, operating at 8.0 Gb/s/pin and 0.3-V transmitter swing without receiver termination to achieve 0.56-pJ/bit energy efficiency and 1.6-Tb/s/mm2 bandwidth density. Measurements of the fabricated SiP validate the functionality and performance of the cores, on-die data bus, and inter-chiplet link. The built-in LIPINCON eye-scan feature validates inter-chiplet connectivity at 8.0 Gb/s with an eye opening of 244 mV and 0.69 UI.

中文翻译：

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用于高性能计算的基于 7-nm 4-GHz Arm^1-Core 的 CoWoS^1 小芯片设计

我们展示了一种基于双芯片内插器的系统级封装 (SiP) 八核处理器，该处理器使用基板上芯片 (CoWoS) 技术。两个相同的小芯片中的每一个都在具有 15 个金属层的 7 纳米 CMOS 中实现，并具有四个以 4.0 GHz 运行的 Arm Cortex-A72 处理器内核。具有 2 毫米触发器到触发器距离的双向网状总线分布在整个小芯片中，用于 4.0 GHz 以上的高速片上数据传输。这些小芯片使用低电压封装内互连 (LIPINCON) 时钟转发并行接口通过超短距离（0.5 毫米长）中介层通道相互通信。可扩展链路模块提供 320 GB/s 的总带宽，以 8.0 Gb/s/pin 和 0.3-V 发射器摆幅运行，无需接收器端接，以实现 0.56-pJ/bit 能效和 1.6-Tb/s/mm2 带宽密度。对制造的 SiP 的测量验证了内核、片上数据总线和芯片间链接的功能和性能。内置的 LIPINCON 眼图扫描功能验证了 8.0 Gb/s 的小芯片间连通性，眼图张开度为 244 mV 和 0.69 UI。