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A 7-nm FinFET CMOS PLL With 388-fs Jitter and -80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control
IEEE Journal of Solid-State Circuits ( IF 5.4 ) Pub Date : 2020-04-01 , DOI: 10.1109/jssc.2019.2959735
Chen-Ting Ko , Ting-Kuei Kuan , Ruei-Pin Shen , Chih-Hsien Chang

This article presents a phase-locked loop (PLL) design that overcomes design challenges imposed by FinFET CMOS nodes, notably high gate resistance and middle-end-of-line parasitics. We propose a track-and-hold charge pump (THCP) and an automatic loop gain control, which not only overcome these challenges but also improve the PLL jitter and reference spur performance. The proposed THCP achieves −115-dBc/Hz in-band phase noise while consuming only $53~\mu \text{W}$ , which is less than 1% of total PLL power consumption. The ring-based PLL achieves both 388-fsrms integrated jitter and reference spurs at −80 dBc. At 4.0 GHz, this PLL consumes 5.9 mW from a 0.9-V supply, translating to a figure of merit of −240.5 dB. The PLL is fabricated in the TSMC 7-nm FinFET CMOS technology.

中文翻译:

具有 388-fs 抖动和 -80-dBc 参考杂散的 7-nm FinFET CMOS PLL,具有跟踪保持电荷泵和自动环路增益控制

本文介绍了一种锁相环 (PLL) 设计,该设计克服了 FinFET CMOS 节点带来的设计挑战,尤其是高栅极电阻和中端寄生效应。我们提出了一种跟踪保持电荷泵 (THCP) 和一种自动环路增益控制,它不仅可以克服这些挑战,还可以改善 PLL 抖动和参考杂散性能。所提出的 THCP 实现了 −115-dBc/Hz 带内相位噪声,同时仅消耗了 $53~\mu\text{W}$,不到 PLL 总功耗的 1%。基于环的 PLL 在 −80 dBc 下实现了 388-fsrms 集成抖动和参考杂散。在 4.0 GHz 时,该 PLL 从 0.9-V 电源消耗 5.9 mW,转换为 -240.5 dB 的品质因数。PLL 采用 TSMC 7-nm FinFET CMOS 技术制造。
更新日期:2020-04-01
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