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A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET
IEEE Journal of Solid-State Circuits ( IF 5.4 ) Pub Date : 2020-04-01 , DOI: 10.1109/jssc.2019.2962655
Armin Tajalli , Mani Bastani Parizi , Dario Albino Carnelli , Chen Cao , Kiarash Gharibdoust , Davide Gorret , Amit Gupta , Christopher Hall , Ahmed Hassanin , Klaas L. Hofstra , Brian Holden , Ali Hormati , John Keay , Yohann Mogentale , Victor Perrin , John Phillips , Sumathi Raparthy , Amin Shokrollahi , David Stauffer , Richard Simpson , Andrew Stewart , Giuseppe Surace , Omid Talebi Amiri , Emanuele Truffa , Anton Tschank , Roger Ulrich , Christoph Walter , Anant Singh

An energy-efficient (1.02 pJ/b) and high-speed (20.83 Gb/s/wire, 417 Gb/s/mm) link for ultra-short reach (USR) applications (up to 6-dB channel loss at the Nyquist frequency of 12.5 GHz) is presented. Correlated non-return to zero (CNRZ) signaling with low sensitivity to inter-symbol interference (ISI) has been developed to improve the link budget. In addition to high pin efficiency (5b6w: 5 bits over 6 wires), the proposed signaling method provides very good resistance against common-mode and crosstalk noise sources, allowing for dense routing. A very wide-band (1.3 GHz) jitter tracking mechanism has been employed to reduce the sensitivity of the system to random and deterministic jitter and relax design constraints on transmitter. A slicer with low kick-back noise and a circuit topology well matched to the continuous-time linear equalizer (CTLE) has been designed to provide both high input sensitivity and Process, supply Voltage, and Temperature (PVT) variations tolerance. The link operates with more than 22-ps (42.5% UI) eye opening at BER = 1E-15. Calibration loops are running in background for quadrature mismatch error correction, clock and data alignment (CDA), and offset removal.

中文翻译:

1.02-pJ/b 20.83-Gb/s/Wire USR 收发器,在 16-nm FinFET 中使用 CNRZ-5

用于超短距离 (USR) 应用的节能 (1.02 pJ/b) 和高速(20.83 Gb/s/线,417 Gb/s/mm)链路(奈奎斯特频率高达 6-dB 信道损耗) 12.5 GHz 的频率)。已开发出对符号间干扰 (ISI) 具有低敏感性的相关不归零 (CNRZ) 信令以改善链路预算。除了高引脚效率(5b6w:6 条线上的 5 位)之外,所提议的信号方法还提供了对共模和串扰噪声源的非常好的抵抗力,从而实现了密集布线。已采用超宽带 (1.3 GHz) 抖动跟踪机制来降低系统对随机和确定性抖动的敏感度,并放宽对发射机的设计约束。具有低反冲噪声和与连续时间线性均衡器 (CTLE) 良好匹配的电路拓扑结构的切片器旨在提供高输入灵敏度和工艺、电源电压和温度 (PVT) 变化容限。该链路在 BER = 1E-15 时以超过 22 ps (42.5% UI) 的眼图张开运行。校准循环在后台运行,用于正交失配纠错、时钟和数据对齐 (CDA) 以及偏移去除。
更新日期:2020-04-01
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