Exact synthesis is a versatile logic synthesis technique with applications to logic optimization, technology mapping, synthesis for emerging technologies, and cryptography. In recent years, advances in SAT solving have led to a heightened research effort into SAT-based exact synthesis. Advantages of exact synthesis include the use of various constraints (e.g., synthesis of emerging technology circuits). However, although progress has been made, its runtime remains unpredictable. This paper identifies two key points as hurdles to further progress. First, there are open questions regarding the design and implementation of exact synthesis systems, due to the many degrees of freedom. For example, there are different CNF encodings, different symmetry breaks to choose from, and different encodings may be suitable for different domains. Second, SAT-based exact synthesis is difficult to parallelize. Indeed, this is a common drawback of logic synthesis algorithms. This paper proposes four ways to close some open questions and to reduce runtime: 1) quantifying differences between CNF encoding schemes and their impacts on runtime; 2) demonstrating impact of symmetry breaking constraints; 3) showing how directed acyclic graph topology information can be used to decrease runtime; and 4) showing how topology information can be used to leverage parallelism.

中文翻译：

---

基于 SAT 的精确综合：编码、拓扑族和并行性

精确综合是一种通用的逻辑综合技术，可应用于逻辑优化、技术映射、新兴技术综合和密码学。近年来，随着 SAT 求解的进步，人们加大了对基于 SAT 的精确合成的研究力度。精确综合的优点包括使用各种约束（例如，新兴技术电路的综合）。然而，尽管取得了进展，但其运行时间仍然不可预测。本文将两个关键点确定为进一步进展的障碍。首先，由于存在许多自由度，因此在精确合成系统的设计和实现方面存在悬而未决的问题。例如，有不同的 CNF 编码，不同的对称性中断可供选择，不同的编码可能适用于不同的领域。第二，基于 SAT 的精确合成很难并行化。事实上，这是逻辑综合算法的一个常见缺点。本文提出了四种方法来解决一些悬而未决的问题并减少运行时间：1）量化 CNF 编码方案之间的差异及其对运行时间的影响；2) 证明对称破坏约束的影响；3) 展示了如何使用有向无环图拓扑信息来减少运行时间；和 4) 展示如何使用拓扑信息来利用并行性。3) 展示了如何使用有向无环图拓扑信息来减少运行时间；和 4) 展示如何使用拓扑信息来利用并行性。3) 展示了如何使用有向无环图拓扑信息来减少运行时间；和 4) 展示如何使用拓扑信息来利用并行性。