Abstract

The interpolator is designed to determine the maximum signal amplitude in the analog channel of a readout ASIC. The use of an interpolator allows to mitigate the requirements for the sampling frequency of an analog-to-digital converter built into the channel of the readout ASIC. Design process and test results of an interpolator unit implemented by means of a FPGA are described.

中文翻译：

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前端电子设备中用于信号峰值检测的内插器

摘要

内插器设计用于确定读出ASIC的模拟通道中的最大信号幅度。内插器的使用可以减轻对内置在读出ASIC通道中的模数转换器的采样频率的要求。描述了通过FPGA实现的内插器单元的设计过程和测试结果。