The perfect pattern transfer from mask to substrate during the plasma‐etching process is strongly limited by the charging effect on the mask surface, which is increased by the accumulation of negative charges on the surface. These are mainly caused by high‐velocity isotropic electrons impinging on the mask surface faster than ions. These anisotropic ions thus bombard the undesired locations of the mask under the influence of the electric field (E‐field) established by electrons. This problem leads to significant damages to the mask pattern and causes deformations of etched features due to failure pattern transfer. This study examined that electron angular distribution (EAD; relative to the vertical direction, which can be regulated by voltage waveform tailoring) displays a close relationship with the mask pattern damage. Based on a modeling framework that consists of a surface etching module, a surface charging module, and a profile evolution module, the effects of changing the EAD on distributions of spatial E‐field and etching rate were studied focusing on an isolated rough mask hole surface. It is revealed that by narrowing the EAD shape, the E‐field strength and the etching rate around the mask hole edge can be reduced strongly, meanwhile, the number of electrons penetrating into the bottom of the trench can be greatly increased. These developments will supposedly reduce the mask‐pattern damage and improve the etching of high‐aspect‐ratio (HAR) features into the substrate. The simulated evolution rates of profile of a rough mask hole and the profile of E‐field strength inside the hole under various EAD shapes verify the above conclusions. The mechanism behind these results was analyzed systematically. This study provides a significant point for further investigation into the optimization of the etching technique.

中文翻译：

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电子角分布对等离子刻蚀中掩模图形损伤影响的研究

在等离子蚀刻过程中，从掩模到基板的完美图案转移受到掩模表面上的电荷效应的强烈限制，而电荷效应则由于表面上的负电荷积累而增加。这主要是由于高速各向同性的电子以比离子快的速度撞击在掩模表面上。因此，这些各向异性离子会在电场的作用下轰击面罩的不良位置（E场）由电子建立。该问题导致对掩模图案的重大损坏，并且由于故障图案转移而导致蚀刻特征的变形。这项研究检查了电子角度分布（EAD；相对于垂直方向，可以通过电压波形调整来调节）显示出与掩模图案损坏密切相关的情况。基于建模框架，其由表面上蚀刻模块，表面的充电模块，和一个轮廓演化模块，改变空间上的分布的EAD的效果ë进行了研究和-field蚀刻速度聚焦的分离的粗掩模孔表面上。结果表明，通过缩小EAD形状，E可以大大降低掩膜孔边缘周围的场强和蚀刻速率，与此同时，可以大大增加渗透到沟槽底部的电子数量。据推测，这些进展将减少掩模图案的损坏，并改善高纵横比（HAR）特征在基板上的蚀刻。一个粗略的掩模孔的轮廓的模拟进化率和轮廓Ë -场强度在孔内以各种形状EAD验证了上述结论。对这些结果背后的机制进行了系统的分析。这项研究为进一步研究蚀刻技术的优化提供了重要的意义。