This article presents a capacitively coupled voltage-controlled oscillator (VCO)-based sensor readout featuring a hybrid phase-locked loop (PLL)- $\Delta \Sigma $ modulator structure. It leverages phase-locking and phase-frequency detector (PFD) array to concurrently perform quantization and dynamic element matching (DEM), much-reducing hardware/power compared with the existing VCO-based readouts’ counting scheme. A low-cost in-cell data-weighted averaging (DWA) scheme is presented to enable a highly linear tri-level digital-to-analog converter (DAC). Fabricated in 40-nm CMOS, the prototype readout achieves 78-dB SNDR in 10-kHz bandwidth, consuming 4.68 $\mu \text{W}$ and 0.025-mm² active area. With 172-dB Schreier figure of merit, its efficiency advances the state-of-the-art VCO-based readouts by $50\times $ .

中文翻译：

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混合 PLL-Δ ΣM 结构中基于 0.025-mm² 0.8-V 78.5-dB SNDR VCO 的传感器读出电路

本文介绍了一种基于电容耦合压控振荡器 (VCO) 的传感器读数，具有混合锁相环 (PLL)- $\Delta \Sigma $ 调制器结构。它利用锁相和相位频率检测器 (PFD) 阵列同时执行量化和动态元素匹配 (DEM)，与现有的基于 VCO 的读数计数方案相比，大大降低了硬件/功耗。提出了一种低成本的单元内数据加权平均 (DWA) 方案，以实现高度线性的三电平数模转换器 (DAC)。采用 40-nm CMOS 制造，原型读数在 10-kHz 带宽内实现 78-dB SNDR，消耗 4.68 $\mu \text{W}$ 和 0.025-mm ²有效面积。凭借 172-dB Schreier 品质因数，其效率将最先进的基于 VCO 的读数提高了 $50\次 $ .