This article presents a split time-interleaved (TI) successive-approximation register (SAR) analog-to-digital converter (ADC) with digital background timing-skew mismatch calibration. It divides a TI-SAR ADC into two split parts with the same overall sampling rate but different numbers of TI channels. Benefitting from the proposed split TI topology, the timing-skew calibration convergence speed is fast without any extra analog circuits. The input impedance of the overall TI-ADC remains unchanged, which is essential for the preceding driving stage in a high-speed application. We designed a prototype seven-/eight-way split TI-ADC implemented in 28-nm CMOS. After a digital background timing-skew calibration, it reaches a 54.2-dB signal-to-noise-and-distortion ratio (SNDR) and 67.1-dB spurious free dynamic range (SFDR) with a near Nyquist rate input signal and a 2.5-GHz effective resolution bandwidth (ERBW). Furthermore, the power consumption of ADC core (mismatch calibration off-chip) is 12.2-mW running at 1.6 GS/s, leading to a Walden figure-of-merit (FOM) of 18.2 fJ/conv.-step and a Schreier FOM of 162.4 dB, respectively.

中文翻译：

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1.6-GS/s 12.2-mW 七路/八路分时交错 SAR ADC，通过数字背景时序失配校准实现 54.2dB SNDR

本文介绍了一种具有数字背景时序偏斜失配校准的分割时间交错 (TI) 逐次逼近寄存器 (SAR) 模数转换器 (ADC)。它将一个 TI-SAR ADC 分成具有相同总体采样率但 TI 通道数不同的两个分割部分。受益于建议的分离 TI 拓扑，时序偏移校准收敛速度很快，无需任何额外的模拟电路。整个 TI-ADC 的输入阻抗保持不变，这对于高速应用中的前一驱动级至关重要。我们设计了一个在 28-nm CMOS 中实现的原型七路/八路分离式 TI-ADC。经过数字背景时间偏差校准后，它达到了 54.2-dB 的信噪比 (SNDR) 和 67。1dB 无杂散动态范围 (SFDR)，具有近奈奎斯特速率输入信号和 2.5GHz 有效分辨率带宽 (ERBW)。此外，ADC 内核（片外失配校准）的功耗为 12.2-mW，运行速度为 1.6 GS/s，导致 Walden 品质因数 (FOM) 为 18.2 fJ/conv.-step 和 Schreier FOM分别为 162.4 dB。