Resilient circuits based on in situ timing monitoring adaptive voltage–frequency scaling (AVFS) eliminate excess time margins caused by process, voltage, and temperature (PVT) variations but suffer from 50% throughput loss during error recovery when operating at a half frequency. We propose a bi-directional adaptive clocking circuit to provide fine frequency tuning with zero latency for AVFS system. It can either stretch the clock cycle when there are timing errors to ensure correct function or compress the cycle when there are excess timing margins. To support a wide frequency range, we generate multiple phase clocks based on two delay lines and select one appropriate phase clock to obtain a stretched output clock, where balanced clock paths are obtained by a time-to-digital converter and dynamic-OR gates. Applied to a wide-operating-range AVFS system of an SHA-256 accelerator with transition detector (TD) latches, the whole AVFS system is able to respond to errors in one clock cycle, with dynamic-OR gates collecting all the errors in half a cycle and adaptive clocking circuit stretching at the current cycle. Fabricated in 28-nm CMOS, chip measurement shows that it achieves 38.6%–69.4% power gains at near threshold while reducing throughput loss during error recovery.

中文翻译：

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28 纳米宽 AVFS 系统中的双向、零延迟自适应时钟电路

基于原位定时监控自适应电压-频率缩放 (AVFS) 的弹性电路消除了由工艺、电压和温度 (PVT) 变化引起的多余时间裕度，但在以半频运行时在错误恢复期间会遭受 50% 的吞吐量损失。我们提出了一种双向自适应时钟电路，为 AVFS 系统提供零延迟的精细频率调谐。它可以在出现时序错误时延长时钟周期以确保正确的功能，或者在时序余量过多时压缩周期。为了支持较宽的频率范围，我们基于两条延迟线生成多个相位时钟，并选择一个合适的相位时钟以获得扩展的输出时钟，其中平衡时钟路径由时间数字转换器和动态或门获得。应用于具有转换检测器 (TD) 锁存器的 SHA-256 加速器的宽操作范围 AVFS 系统，整个 AVFS 系统能够在一个时钟周期内响应错误，动态或门将所有错误收集一半一个周期和自适应时钟电路在当前周期延伸。采用 28 纳米 CMOS 制造的芯片测量表明，它在接近阈值时实现了 38.6%–69.4% 的功率增益，同时减少了错误恢复期间的吞吐量损失。