This paper provides the essential details of implementing 4-phase bundled data and speed independent asynchronous circuits on FPGAs. The required Xilinx synthesis tools including attributes, constraints and hardware implementation of basic asynchronous elements like Cgate, delay line, and handshaking modules are discussed. Finally, two design and implementation examples of asynchronous circuits are introduced. In order to reduce area and energy overhead, an N-stage pipeline with internal loops is proposed and employed in asynchronous Fuzzy Logic Controller (FLC). It is observed that synchronous FLC operating at 100 MHz consumes 27% more dynamic power while occupying 23% fewer FPGA resources compared to its asynchronous counterpart. At the same time, the asynchronous circuit has obtained an improvement of 19% in FLC performance compared to synchronous FLC. The other implementation example explains the technical details of the design and implementation process of speed independent circuit using Petrify and ISE at the LUT level. Both design examples are implemented and tested successfully on FPGA board.

本文提供了在FPGA上实现4相捆绑数据和速度独立异步电路的基本细节。讨论了所需的Xilinx综合工具，包括基本异步元素（如Cgate，延迟线和握手模块）的属性，约束和硬件实现。最后，介绍了异步电路的两个设计和实现示例。为了减少面积和能源开销，提出了一种带有内部回路的N级管线，并在异步模糊逻辑控制器（FLC）中使用。可以看出，与异步同步FLC相比，工作在100 MHz的同步FLC消耗的动态功耗高27％，而FPGA资源却减少23％。同时，与同步FLC相比，异步电路的FLC性能提高了19％。另一个实现示例说明了在LUT级别使用Petrify和ISE的速度独立电路的设计和实现过程的技术细节。这两个设计实例均在FPGA板上成功实现并测试。