Wide bandgap (WBG) devices allow power factor correction (PFC) circuits to operate at megahertz (MHz), which improves power density. In low-power applications, critical conduction mode (CrM) boost PFC circuits are widely used due to its simple structure and minimized turn-on loss. Compared with the kilohertz (kHz) operation, MHz PFC in CrM yields larger inductor valley current during the zero voltage or valley switching turn-on, and significant grid current zero-crossing distortion, both of which are not considered in conventional PFC behavioral models. As a result, the conventional PFC design tool shows substantial inaccuracy in the estimation of switching frequency, inductor current envelopes, and power loss. This article analyzes these issues and proposes an improved power loss model to aid the design of MHz CrM PFC. Experimental results are presented to validate the accuracy.

中文翻译：

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GaN基MHz临界传导模式功率因数校正电路的功率损耗模型

宽带隙（WBG）器件允许功率因数校正（PFC）电路以兆赫兹（MHz）运行，从而提高了功率密度。在低功率应用中，临界传导模式（CrM）升压PFC电路由于其简单的结构和最小的导通损耗而被广泛使用。与千赫（kHz）操作相比，CrM中的MHz PFC在零电压或谷底开关导通期间产生更大的电感器谷底电流，以及显着的电网电流过零失真，这在常规PFC行为模型中均未考虑。结果，传统的PFC设计工具在估计开关频率，电感器电流包络和功率损耗时显示出很大的误差。本文对这些问题进行了分析，并提出了一种改进的功率损耗模型，以帮助设计MHz CrM PFC。