Wide bandgap (WBG) power devices with voltage ratings exceeding 10 kV have the potential to revolutionize medium- and high-voltage systems due to their high-speed switching and lower ON-state losses. However, the present power module packages are limiting the performance of these unique switches. The objective of this article is to push the boundaries of high-density, high-speed, 10-kV power module packaging. The proposed package addresses the well-known electromagnetic and thermal challenges, as well as the more recent and prominent electrostatic and electromagnetic interference (EMI) issues associated with high-speed, 10-kV devices. The module achieves low and balanced parasitic inductances, resulting in a record switching speed of 250 V/ns with negligible ringing and voltage overshoot. An integrated screen reduces the common-mode (CM) current that is generated by these fast voltage transients by ten times. This screen connection simultaneously increases the partial discharge inception voltage (PDIV) by more than 50%. A compact, medium-voltage termination and system interface design is also proposed in this article. With the integrated jet-impingement cooler, the power module prototype achieves a power density of 4 W/mm ³ . This article presents the design, prototyping, and testing of this optimized package for 10-kV SiC MOSFETs.

中文翻译：

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少焊线的10kV SiC MOSFET功率模块的设计和实验验证

额定电压超过10 kV的宽带隙（WBG）功率设备具有高速开关和较低的导通损耗，因此有可能改变中高压系统。然而，当前的功率模块封装限制了这些独特的开关的性能。本文的目的是突破高密度，高速，10kV电源模块封装的界限。提议的封装解决了众所周知的电磁和热挑战，以及与高速10 kV设备相关的最新和突出的静电和电磁干扰（EMI）问题。该模块实现了低且平衡的寄生电感，从而创纪录的250 V / ns的开关速度，而振铃和电压过冲可忽略不计。集成屏幕将这些快速电压瞬变产生的共模（CM）电流降低了十倍。这种屏蔽连接可同时将部分放电起始电压（PDIV）提高50％以上。本文还提出了一种紧凑的中压终端和系统接口设计。借助集成的射流冷却器，电源模块原型可实现4 W / mm的功率密度 ³ 。本文介绍了针对10 kV SiC MOSFET的这种优化封装的设计，原型设计和测试。