For increasing the restricted bit-density in the conventional binary logic system, extensive research efforts have been directed toward implementing single devices with a two threshold voltage (V_TH) characteristic via the single negative differential resistance (NDR) phenomenon. In particular, recent advances in forming van der Waals (vdW) heterostructures with two-dimensional crystals have opened up new possibilities for realizing such NDR-based tunneling devices. However, it has been challenging to exhibit three V_TH through the multiple-NDR (m-NDR) phenomenon in a single device even by using vdW heterostructures. Here, we show the m-NDR device formed on a BP/(ReS₂ + HfS₂) type-III double-heterostructure. This m-NDR device is then integrated with a vdW transistor to demonstrate a ternary vdW latch circuit capable of storing three logic states. Finally, the ternary latch is extended toward ternary SRAM, and its high-speed write and read operations are theoretically verified.

中文翻译：

---

多重负差分电阻异质结器件及其电路在三态静态随机存取存储器中的应用

为了增加常规二进制逻辑系统中的受限位密度，已经针对通过单个负差分电阻（NDR）现象实现具有两个阈值电压（V _TH）特性的单个器件进行了广泛的研究。特别地，利用二维晶体形成范德华（vdW）异质结构的最新进展为实现这种基于NDR的隧穿器件开辟了新的可能性。然而，即使通过使用vdW异质结构，在单个器件中通过多重NDR（m-NDR）现象表现出三个V _TH仍然具有挑战性。在这里，我们显示了在BP /（ReS ₂ + HfS ₂）III型双异质结构。然后将此m-NDR器件与vdW晶体管集成在一起，以演示能够存储三个逻辑状态的三元vdW锁存电路。最后，将三元锁存器扩展到三元SRAM，并从理论上验证了其高速写入和读取操作。