Two main bottlenecks encountered when implementing energy-efficient spike-timing-dependent plasticity (STDP) based sparse coding, are the complex computation of winner-take-all (WTA) operation and repetitive neuronal operations in the time domain processing. In this article, we present an energy-efficient STDP based sparse coding processor. The low-cost hardware is based on the algorithmic reduction techniques as following: First, the complex WTA operation is simplified based on the prediction of spike emitting neurons. Sparsity based approximation in spatial and temporal domain are also efficiently exploited to remove the redundant neurons with negligible algorithmic accuracy loss. We designed and implemented the hardware of the STDP based sparse coding using 65nm CMOS process. By exploiting input sparsity, the proposed SNN architecture can dynamically trade off algorithmic quality for computation energy (up to 74%) for Natural image (maximum 0.01 RMSE increment) and MNIST (no accuracy loss) applications. In the inference mode of operations, the SNN hardware achieves the throughput of 374 Mpixels/s and 840.2 GSOP/s with the energy-efficiency of 781.52 pJ/pixel and 0.35 pJ/SOP.

中文翻译：

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具有片上学习能力的基于能量质量可扩展STDP的稀疏编码处理器

实施基于节能的基于时序的依赖于时机的可塑性（STDP）的稀疏编码时遇到的两个主要瓶颈是时域处理中胜者通吃（WTA）操作和重复性神经元操作的复杂计算。在本文中，我们提出了一种基于节能STDP的稀疏编码处理器。低成本硬件基于以下算法缩减技术：首先，基于对尖峰发射神经元的预测，简化了复杂的WTA操作。还有效地利用了时空域中基于稀疏性的近似值，以消除算法精度损失可忽略的冗余神经元。我们使用65nm CMOS工艺设计并实现了基于STDP的稀疏编码的硬件。通过利用输入稀疏性，对于自然图像（最大0.01 RMSE增量）和MNIST（无精度损失）应用，所提出的SNN体系结构可以动态地权衡算法质量（高达74％）的计算能力。在推理操作模式下，SNN硬件实现了374 Mpixels / s和840.2 GSOP / s的吞吐量，能量效率为781.52 pJ / pixel和0.35 pJ / SOP。