Predictable execution time upon accessing shared memories in multi-core real-time systems is a stringent requirement. A plethora of existing works focus on the analysis of Double Data Rate Dynamic Random Access Memories (DDR DRAMs), or redesigning its memory to provide predictable memory behavior. In this paper, we show that DDR DRAMs by construction suffer inherent limitations associated with achieving such predictability. These limitations lead to (1) highly variable access latencies that fluctuate based on various factors such as access patterns and memory state from previous accesses, and (2) overly pessimistic latency bounds. As a result, DDR DRAMs can be ill-suited for some real-time systems that mandate a strict predictable performance with tight timing constraints. Targeting these systems, we promote an alternative off-chip memory solution that is based on the emerging Reduced Latency DRAM (RLDRAM) protocol, and propose a predictable memory controller (RLDC) managing accesses to this memory. Comparing with the state-of-the-art predictable DDR controllers, the proposed solution provides up to $$\mathbf{11 }\times $$ 11 × less timing variability and $$\mathbf{6.4 }\times $$ 6.4 × reduction in the worst case memory latency.

中文翻译：

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减少多核安全关键实时系统的延迟 DRAM

在多核实时系统中访问共享内存时的可预测执行时间是一项严格的要求。大量现有工作侧重于双倍数据速率动态随机存取存储器 (DDR DRAM) 的分析，或重新设计其存储器以提供可预测的存储器行为。在本文中，我们展示了 DDR DRAM 的构造受到与实现这种可预测性相关的固有限制。这些限制导致 (1) 高度可变的访问延迟，这些访问延迟会根据各种因素波动，例如访问模式和先前访问的内存状态，以及 (2) 过于悲观的延迟界限。因此，DDR DRAM 可能不适合某些要求严格的可预测性能和严格时序约束的实时系统。针对这些系统，我们推广了一种基于新兴的低延迟 DRAM (RLDRAM) 协议的替代片外存储器解决方案，并提出了一种可预测的存储器控​​制器 (RLDC)，用于管理对该存储器的访问。与最先进的可预测 DDR 控制器相比，所提出的解决方案提供高达 $$\mathbf{11 }\times $$ 11 × 更少的时序可变性和 $$\mathbf{6.4 }\times $$ 6.4 ×减少最坏情况下的内存延迟。