Copper is the primary metal used in integrated circuit manufacturing of today. Even though copper is face centered cubic it has significant mechanical anisotropy depending on the crystallographic orientations. Copper metal lines in integrated circuits are polycrystalline and typically have lognormal grain size distribution. The polycrystalline microstructure is known to impact the reliability and must be considered in modeling for better understanding of the failure mechanisms. In this work, we used Voronoi tessellation to model the polycrystalline microstructure with lognormal grainsize distribution for the copper metal lines in test structures. Each of the grains is then assigned an orientation with distinct probabilistic texture and corresponding anisotropic elastic constants based on the assigned orientation. The test structure is then subjected to a thermal stress. A significant variation in hydrostatic stresses at the grain boundaries is observed by subjecting the test structure to thermal stress due to the elastic anisotropy of copper. This introduces new weak points within the metal interconnects leading to failure. Inclusion of microstructures and corresponding anisotropic properties for copper grains is crucial to conduct a realistic study of stress voiding, hillock formation, delamination, and electromigration phenomena, especially at smaller nodes where the anisotropic effects are significant.

中文翻译：

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对铜的微观结构和弹性各向异性进行建模，并研究其对纳米级互连中可靠性的影响

铜是当今集成电路制造中使用的主要金属。即使铜的面心立方，它也具有很大的机械各向异性，具体取决于晶体学取向。集成电路中的铜金属线是多晶的，通常具有对数正态粒度分布。众所周知，多晶微结构会影响可靠性，因此在建模中必须考虑多晶微结构，以更好地了解失效机理。在这项工作中，我们使用Voronoi镶嵌来模拟测试结构中铜金属线具有对数正态粒度分布的多晶微观结构。然后，根据指定的方向为每个晶粒分配具有不同概率纹理的方向以及相应的各向异性弹性常数。然后使测试结构经受热应力。通过使测试结构受到铜的弹性各向异性引起的热应力，可以观察到晶界处静水压力的显着变化。这会在金属互连中引入新的弱点，从而导致故障。包含铜晶粒的微观结构和相应的各向异性特性对于进行应力空洞，小丘形成，分层和电迁移现象的现实研究至关重要，尤其是在各向异性效果显着的较小节点处。这会在金属互连中引入新的弱点，从而导致故障。包含铜晶粒的微观结构和相应的各向异性特性对于进行应力空洞，小丘形成，分层和电迁移现象的现实研究至关重要，尤其是在各向异性效果显着的较小节点处。这会在金属互连中引入新的弱点，从而导致故障。包含铜晶粒的微观结构和相应的各向异性特性对于进行应力空洞，小丘形成，分层和电迁移现象的现实研究至关重要，尤其是在各向异性效果显着的较小节点处。