On-chip global interconnects are becoming speed and power bottlenecks in state-of-the-art chips. Low-swing signaling is used to improve delay performance and reduce power consumption. This paper first performs a delay analysis for different low-swing circuits based on the Asymptotic Waveform Evaluation (AWE). In addition, new delay metrics are presented and analyzed. The new delay metrics demonstrate that optimal designs can be obtained in low-swing signaling. To verify our analysis, a simulation environment is established. The simulation results indicate that the optimal designs can increase the 3[Formula: see text]dB bandwidth of a wire by more than 40% in resistively driven or capacitively driven 10[Formula: see text]mm global links. Thus, these optimal design methods can effectively improve the bandwidth of global wires.

中文翻译：

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低摆幅 RC-Limited 全局互连的延迟分析和设计优化

片上全球互连正在成为最先进芯片的速度和功率瓶颈。低摆幅信令用于提高延迟性能并降低功耗。本文首先基于渐近波形评估（AWE）对不同的低摆幅电路进行延迟分析。此外，还提出并分析了新的延迟指标。新的延迟度量表明，可以在低摆幅信号中获得最佳设计。为了验证我们的分析，我们建立了一个仿真环境。仿真结果表明，在电阻驱动或电容驱动的 10[公式：见文本]mm 全局链路中，优化设计可以将导线的 3[公式：见文本]d​​B 带宽提高 40% 以上。因此，这些优化设计方法可以有效地提高全局导线的带宽。