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Self-Heating in 40nm SOI MOSFETs on High Resistivity, Trap-Rich Substrates
IEEE Transactions on Nanotechnology ( IF 2.4 ) Pub Date : 2020-01-01 , DOI: 10.1109/tnano.2019.2952759
Xiong Zhang , Payam Mehr , Trevor J. Thornton

Closely spaced n-channel MOSFETs have been used to compare the self-heating in nominally identical devices fabricated on conventional and high resistivity, trap-rich silicon-on-insulator (SOI) substrates. One of the MOSFETs operates above threshold and in saturation to heat the active silicon, while the other is biased into the sub-threshold regime and operates as a local thermometer. The trap-rich layer in the high resistivity substrates consists of a highly defected, poly-Si layer just below the buried oxide. Grain boundaries in the poly-Si lead to increased phonon scattering compared to single crystal silicon, with a corresponding decrease in thermal conductivity. Despite the reduced thermal conductivity there appears to be no difference in the self-heating between the MOSFETs on the high resistivity, trap-rich substrates compared to those on the conventional low resistivity substrates.

中文翻译:

40nm SOI MOSFET 在高电阻率、富陷阱衬底上的自发热

紧密间隔的 n 沟道 MOSFET 已用于比较在传统和高电阻率、富含陷阱的绝缘体上硅 (SOI) 衬底上制造的名义上相同的器件中的自热。其中一个 MOSFET 工作在阈值以上并处于饱和状态以加热有源硅,而另一个则被偏置到亚阈值状态并作为本地温度计工作。高电阻率衬底中的富陷阱层由掩埋氧化物正下方的高度缺陷多晶硅层组成。与单晶硅相比,多晶硅中的晶界导致声子散射增加,热导率相应降低。尽管热导率降低,但在高电阻率下,MOSFET 之间的自热似乎没有差异,
更新日期:2020-01-01
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