Abstract

This paper proposes a full-transistor multilevel delay element (DE) implemented by 65 nm/1.8 V CMOS technology. 10 mV/LSB and 50 mV/LSB control voltages are employed to realize the fine-grain and coarse tuning for multilevel delay adjustment while maintain the duty cycle of input pulse. In physical design, a novel transistor array with a compact regularity layout is adopted to mitigate process variation. According to the post-layout simulation analysis, compared with two traditional delay elements, the proposed DE has particular advantages in terms of the layout area as well as achieves the acceptable merely 2× power consumption and 22.9% delay quantization error in linearity accuracy. The effective 2 MHz bandwidth and nano-second delay range is applicable to a low/medium frequency clock compensation system.

中文翻译：

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具有紧凑规则布局的全晶体管细粒度多级延迟元件

摘要

本文提出了一种采用65 nm / 1.8 V CMOS技术实现的全晶体管多级延迟元件（DE）。采用10 mV / LSB和50 mV / LSB控制电压来实现微调和粗调，以进行多级延迟调整，同时保持输入脉冲的占空比。在物理设计中，采用具有紧凑规则布局的新型晶体管阵列来减轻工艺变化。根据布局后的仿真分析，与两个传统的延迟元素相比，所提出的DE在布局面积方面具有特殊优势，并且在线性精度方面仅实现了可接受的2倍功耗和22.9％的延迟量化误差。有效的2 MHz带宽和纳秒延迟范围适用于中低频率时钟补偿系统。