Abstract

This paper describes a readout IC (ROIC), which consists of a capacitively coupled instrumentation amplifier (CCIA) and a discrete-time delta–sigma modulator. An active high-pass filter is embedded in the ripple reduction loop to suppress the noise ripple amplitude due to chop modulation. To accommodate the input with large electrode offset, dc-servo loop (DSL) and a 6 bit capacitive DAC are employed to suppress large electrode offset, while a positive feedback loop to boost its input impedance. The complete CCIA is implemented in a standard 0.18 μm 1P6M CMOS process. It occupies an area of 0.56 mm² (including DSL) and consumes 52 μA current from a 3.3 V supply voltage. Measurement results indicate that the input reference noise PSD is 53.8 nV√Hz.

中文翻译：

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采用0.18μmCMOS工艺的电容耦合斩波器电流反馈仪表放大器的读出IC设计

摘要

本文介绍了一种读出IC（ROIC），它由一个电容耦合仪表放大器（CCIA）和一个离散时间delta-sigma调制器组成。有源高通滤波器嵌入到纹波减小环路中，以抑制由于斩波调制而引起的噪声纹波幅度。为了适应具有较大电极偏移的输入，采用了直流伺服环路（DSL）和6位电容DAC来抑制较大的电极偏移，同时采用正反馈环路来提高其输入阻抗。完整的CCIA以标准的0.18μm1P6M CMOS工艺实现。它占用的面积为0.56 mm ²（包括DSL），并通过3.3 V电源电压消耗52μA电流。测量结果表明，输入参考噪声PSD为53.8nV√Hz。