Synchoros VLSI design style has been proposed as an alternative to standard cell-based design. Standard cells are replaced by synchoros large grain VLSI design objects called SiLago blocks. This new design style enables end-to-end automation of large scale designs by abutting the SiLago blocks to eliminate logic and physical synthesis for the end-users. A key problem in this automation process is the generation of regional clock tree. Synchoros design style requires that the clock tree should emerge by abutting its fragments. The clock tree fragments are absorbed in the SiLago blocks as a one-time engineering effort. The clock tree should not be ad-hoc, but a structured and predictable design whose cost metrics are known. Here, we present a new clock tree design that is compatible with the synchoros design style. The proposed design has been verified with static timing analysis and compared against functionally equivalent clock tree synthesised by the commercial EDA tools. The scheme is scalable and, in principle, can generate arbitrarily complex designs. In this paper, we show as a proof of concept that a regional clock tree can be created by abutment. We prove that with the help of the generated clock tree, it is possible to generate valid VLSI designs from 0.5 to ~2 million gates. The resulting generated designs do not need a separate regional clock tree synthesis. More critically, the synthesised design is correct by construction and requires no further verification. In contrast, the state-of-the-art hierarchical synthesis flow requires synthesis of the regional clock tree. Additionally, the conventional clock tree and its design needs a verification step because it lacks predictability. The results also demonstrate that the capacitance, slew and the ability to balance skew of the clock tree created by abutment is comparable to the one generated by commercial EDA tools.

中文翻译：

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Synchoros VLSI 设计中通过桥台生成区域时钟树

Synchoros VLSI 设计风格已被提议作为基于标准单元的设计的替代方案。标准单元被称为 SiLago 块的同步大颗粒 VLSI 设计对象所取代。这种新的设计风格通过邻接 SiLago 块来实现大规模设计的端到端自动化，从而为最终用户消除逻辑和物理综合。这个自动化过程中的一个关键问题是区域时钟树的生成。Synchoros 设计风格要求时钟树应通过邻接其片段而出现。时钟树片段作为一次性工程工作被吸收到 SiLago 块中。时钟树不应该是临时的，而是一个结构化和可预测的设计，其成本指标是已知的。在这里，我们展示了一种与同步设计风格兼容的新时钟树设计。所提出的设计已经通过静态时序分析进行了验证，并与由商业 EDA 工具合成的功能等效的时钟树进行了比较。该方案是可扩展的，原则上可以生成任意复杂的设计。在本文中，我们展示了可以通过基台创建区域时钟树的概念证明。我们证明，在生成的时钟树的帮助下，可以生成从 0.5 到 ~200 万门的有效 VLSI 设计。生成的设计不需要单独的区域时钟树综合。更重要的是，综合设计在构造上是正确的，不需要进一步验证。相比之下，最先进的分层综合流程需要综合区域时钟树。此外，传统的时钟树及其设计需要一个验证步骤，因为它缺乏可预测性。结果还表明，由邻接创建的时钟树的电容、转换和平衡能力与商业 EDA 工具生成的时钟树相媲美。