A new circuit of delay cell for differential ring oscillator (DRO), to generate wide tuning range, has been proposed. Two architectures of DRO: 3 stage and 4 stage, have been designed and simulated under the power supply constraint of 1.1 V, using GPDK 45 nm CMOS technology. Dual voltages are used to control the tuning frequency range in 3 stage DRO whereas single voltage control is used in 4 stage DRO. Tuning ranges of 351 MHz–30.33 GHz and 574 MHz–20.49 GHz, are generated using the proposed 3-stage and 4-stage DRO circuits, respectively. Total Harmonic Distortion of both circuits, is also measured through simulation. Power consumption of the proposed 3-stage and 4 stage DRO, are found to be 866 μW and 783 μW at an oscillation frequency of 2.77 GHz and 1.86 GHz, respectively. Proposed circuits exhibit phase noise of − 96.7 dBc/Hz and − 99.54 dBc/Hz at an offset of 10 MHz from the frequency of oscillation. Layout, is also drawn, occupies an area of 137.97 μm² and 170.34 μm² for 3 stage and 4 stage DRO, respectively. Robustness of the proposed circuits are verified across Process, Voltage and Temperature variations. The proposed DROs exhibit the largest tuning range when compared with the recent literature.

提出了一种用于差分环形振荡器（DRO）的延迟单元的新电路，以产生宽调谐范围。使用GPDK 45 nm CMOS技术，在1.1 V的电源约束下设计和仿真了DRO的两种体系结构：3级和4级。双电压用于控制3级DRO中的调谐频率范围，而单电压控制用于4级DRO中。分别使用建议的3级和4级DRO电路生成351 MHz–30.33 GHz和574 MHz–20.49 GHz的调谐范围。两个电路的总谐波失真也通过仿真来测量。所提出的3级和4级DRO的功耗在2.77 GHz和1.86 GHz的振荡频率下分别为866μW和783μW。拟议的电路表现出− 96.7 dBc / Hz和− 99的相位噪声。与振荡频率的偏移量为10 MHz时为54 dBc / Hz。还绘制了版图，其面积为137.97μm²和170.34微米²为分别3阶段和第4阶段DRO，。所提出的电路的鲁棒性在工艺，电压和温度变化范围内得到了验证。与最新文献相比，提出的DRO具有最大的调谐范围。