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A Bunch of Wires (BoW) Interface for Inter-Chiplet Communication
IEEE Micro ( IF 3.6 ) Pub Date : 2020-01-01 , DOI: 10.1109/mm.2019.2950352
Ramin Farjadrad , Mark Kuemerle , Bapi Vinnakota

Multichiplet system-in-package designs have recently received a lot of attention as a mechanism to combat high SoC design costs and to economically manufacture large ASICs. These designs require low-power area-efficient off-die on-package die-to-die communication. Current technologies either extend on-die high-wire count buses using silicon interposers or off-package serial buses. The former approach leads to expensive packaging. The latter leads to complex and high-power designs. We propose a simple bunch-of-wires interface that combines ease of development with low-cost packaging techniques. We develop the interface and show how it can be used in multichiplet systems.

中文翻译:

用于芯片间通信的一组电线 (BoW) 接口

多芯片系统级封装设计作为一种对抗高 SoC 设计成本和经济地制造大型 ASIC 的机制,最近受到了很多关注。这些设计需要低功耗、面积高效的芯片外封装上芯片到芯片通信。当前的技术要么使用硅中介层扩展芯片上高线数总线,要么使用封装外串行总线。前一种方法导致昂贵的封装。后者导致复杂且高功率的设计。我们提出了一种简单的线束接口,它将易于开发与低成本封装技术相结合。我们开发了接口并展示了如何在多芯片系统中使用它。
更新日期:2020-01-01
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