HPC architects are currently facing myriad challenges from ever tighter power constraints and changing workload characteristics. In this article, we discuss the current state of FPGAs within HPC systems. Recent technological advances show that they are well placed for penetration into the HPC market. However, there are still a number of research problems to overcome; we address the requirements for system architectures and interconnects to enable their proper exploitation, highlighting the necessity of allowing FPGAs to act as full-fledged peers within a distributed system rather than attached to the CPU. We argue that this model requires a reliable, connectionless, hardware-offloaded transport supporting a global memory space. Our results show how our fully fledged hardware implementation gives latency improvements of up to 25% versus a software-based transport, and demonstrates that our solution can outperform the state of the art in HPC workloads such as matrix–matrix multiplication achieving a 10% higher computing throughput.

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为基于 FPGA 的 HPC 提供案例

HPC 架构师目前正面临着来自日益严格的功率限制和不断变化的工作负载特性的无数挑战。在本文中，我们将讨论 HPC 系统中 FPGA 的当前状态。最近的技术进步表明，它们已准备好进入 HPC 市场。然而，仍有许多研究问题需要克服；我们解决了对系统架构和互连的要求，以使其能够正确利用，强调了允许 FPGA 在分布式系统中充当成熟对等体而不是连接到 CPU 的必要性。我们认为该模型需要支持全局内存空间的可靠、无连接、硬件卸载的传输。