The risk of soft errors due to radiation continues to be a significant challenge for engineers trying to build systems that can handle harsh environments. Building systems that are Radiation Hardened by Design (RHBD) is the preferred approach, but existing techniques are expensive in terms of performance, power, and/or area. This paper introduces a novel soft-error resilient asynchronous bundled-data design template, SERAD, which uses a combination of temporal and spatial redundancy to mitigate Single Event Transients (SETs) and upsets (SEUs). SERAD uses Error Detecting Logic (EDL) to detect SETs at the inputs of sequential elements and correct them via re-sampling. Because SERAD only pays the delay penalty in the presence of an SET, which rarely occurs, its average performance is comparable to the baseline synchronous design. We tested the SERAD design using a combination of Spice and Verilog simulations and evaluated its impact on area, frequency, and power on an open-core MIPS-like processor using a NCSU 45nm cell library. Our post-synthesis results show that the SERAD design consumes less than half of the area of the Triple Modular Redundancy (TMR), exhibits significantly less performance degradation than Glitch Filtering (GF), and consumes no more total power than the baseline unhardened design.

中文翻译：

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SERAD：使用捆绑数据协议的软错误弹性异步设计

对于试图构建能够处理恶劣环境的系统的工程师来说，由辐射引起的软错误风险仍然是一个重大挑战。构建抗辐射设计 (RHBD) 系统是首选方法，但现有技术在性能、功率和/或面积方面成本高昂。本文介绍了一种新颖的软错误弹性异步捆绑数据设计模板 SERAD，它使用时间和空间冗余的组合来减轻单事件瞬态 (SET) 和扰乱 (SEU)。SERAD 使用错误检测逻辑 (EDL) 来检测时序元件输入端的 SET，并通过重新采样来纠正它们。由于 SERAD 仅在 SET 存在时支付延迟损失，这种情况很少发生，因此其平均性能与基线同步设计相当。我们使用 Spice 和 Verilog 模拟的组合测试了 SERAD 设计，并使用 NCSU 45nm 单元库评估了它对类似开放核 MIPS 的处理器的面积、频率和功率的影响。我们的综合后结果表明，SERAD 设计消耗的面积不到三重模块化冗余 (TMR) 面积的一半，与毛刺过滤 (GF) 相比，性能下降明显更小，并且消耗的总功率不超过基线未硬化设计。