Software defined radio is a widely accepted paradigm for design of reconfigurable modems. The continuing march of Moore's law makes real-time signal processing on general purpose processors feasible for a large set of waveforms. Data rates in the low Mbps can be processed on low-power ARM processors, and much higher data rates can be supported on large x86 processors. The advantages of all-software development (vs. FPGA/DSP/GPU) are compelling: much wider pool of talent, lower development time and cost, and easier maintenance and porting. However, very high-rate systems (above 100 Mbps) are still firmly in the domain of custom and semi-custom hardware (mostly FPGAs). In this paper we describe an architecture and testbed for an SDR that can be easily scaled to support over 3 GHz of bandwidth and data rate up to 10 Gbps. The paper covers a novel technique to parallelize typically serial algorithms for phase and symbol tracking, followed by a discussion of data distribution for a massively parallel architecture. We provide a brief description of a mixed-signal front end and conclude with measurement results. To the best of the author's knowledge, the system described in this paper is an order of magnitude faster than any prior published result.

中文翻译：

---

极限软件定义无线电——实时 GHz

软件定义无线电是一种广泛接受的可重构调制解调器设计范例。摩尔定律的不断发展使得在通用处理器上对大量波形进行实时信号处理变得可行。低 Mbps 的数据速率可以在低功耗 ARM 处理器上处理，并且在大型 x86 处理器上可以支持更高的数据速率。全软件开发（相对于 FPGA/DSP/GPU）的优势非常引人注目：更广泛的人才库、更低的开发时间和成本以及更容易的维护和移植。然而，非常高速率的系统（100 Mbps 以上）仍然牢牢占据定制和半定制硬件（主要是 FPGA）领域。在本文中，我们描述了 SDR 的架构和测试平台，可以轻松扩展以支持超过 3 GHz 的带宽和高达 10 Gbps 的数据速率。本文介绍了一种新技术，用于并行化用于相位和符号跟踪的典型串行算法，然后讨论大规模并行架构的数据分布。我们简要描述了混合信号前端，并以测量结果结束。据作者所知，本文中描述的系统比之前发表的任何结果都要快一个数量级。