We demonstrate dual-gated (DG) MoS₂ field effect transistors (FETs) in which the degraded switching performance of multilayer MoS₂ can be compensated by the DG structure. It produces large current density (>100 μA/μm for a monolayer), steep subthreshold swing (SS) (∼100 mV/dec for 5 nm thickness), and high on/off current ratio (>10⁷ for 10 nm thickness). Such DG structure not only improves electrostatic control but also provides an extra degree of freedom for manipulating the threshold voltage (V_TH) and SS by separately tuning the top and back gate voltages, which are demonstrated in a logic inverter. Dynamic random access memory (DRAM) has a short retention time because of large OFF-state current in the Si MOSFET. Based on our DG MoS₂-FETs, a DRAM unit cell with a long retention time of 1260 ms is realized. Large-scale isolated MoS₂ DG-FETs based on CVD-synthesized continuous films are also demonstrated, which show potential applications for future wafer-scale digital and low-power electronics.

中文翻译：

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基于双门MoS ₂架构的高性能逻辑和存储设备

我们演示了双栅极（DG）MoS ₂场效应晶体管（FET），其中多层MoS ₂的降级开关性能可以通过DG结构进行补偿。它产生大电流密度（单层> 100μA/μm），陡峭的亚阈值摆幅（SS）（5 nm厚度约为100 mV / dec）和高开/关电流比（10 nm厚度> 10 ⁷） 。这种DG结构不仅可以改善静电控制效果，而且可以提供更大的自由度来操纵阈值电压（V _TH）和SS分别通过调整顶部和背面栅极电压来实现，这在逻辑反相器中得到了证明。动态随机存取存储器（DRAM）的保留时间短，这是因为Si MOSFET中的截止状态电流很大。基于我们的DG MoS ₂ -FET，可实现具有1260 ms长保留时间的DRAM单元。还展示了基于CVD合成的连续膜的大规模隔离式MoS ₂ DG-FET，它们显示了未来晶圆级数字和低功耗电子产品的潜在应用。