Phase-change memory (PCM) is a non-volatile memory device with favorable characteristics such as persistence, byte-addressability, and lower latency when compared to flash memory. However, it comprises memory cells that have limited lifetime and higher access latency than DRAM. The row buffer size of a PCM is preferred to be larger than 128B to fill the latency gap between two memories and to reduce the metadata overhead incurred by wear leveling. As the cache line size in a general-purpose processor is 64B, a read-modify-write (RMW) module is required to be placed between the processor and the PCM, which in turn induces a performance degradation. To reduce such an overhead and enhance the reliability of a device, this paper presents a new RMW architecture. The proposed model introduces a DRAM cache in the RMW module, which minimizes redundant read operations for write operations by pre-fetching the entire transaction unit instead of merely caching the 64B requested data. Furthermore, a typeless merge operation is performed with the proposed cache by gathering multiple commands accessing consecutive addresses, irrespective of whether they are READ or WRITE. Simulation results indicate that the proposed method enhances the speed by 3.2 times and the reliability by 49 percent as compared to the baseline model.

中文翻译：

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相变存储系统中读写模块的集成与提升

相变存储器 (PCM) 是一种非易失性存储设备，与闪存相比，它具有诸如持久性、字节寻址能力和更低的延迟等优点。然而，它包含的存储单元寿命有限且访问延迟高于 DRAM。PCM 的行缓冲区大小最好大于 128B，以填补两个内存之间的延迟间隙并减少磨损均衡引起的元数据开销。由于通用处理器中的缓存线大小为64B，因此需要在处理器和PCM之间放置读-修改-写（RMW）模块，这反过来会导致性能下降。为了减少这种开销并提高设备的可靠性，本文提出了一种新的 RMW 架构。所提出的模型在 RMW 模块中引入了 DRAM 缓存，它通过预取整个事务单元而不是仅仅缓存 64B 请求的数据来最小化写操作的冗余读操作。此外，通过收集访问连续地址的多个命令，无论它们是 READ 还是 WRITE，对建议的缓存执行无类型合并操作。仿真结果表明，与基线模型相比，所提方法的速度提高了3.2倍，可靠性提高了49%。