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High level programming abstractions for leveraging hierarchical memories with micro-core architectures
Journal of Parallel and Distributed Computing ( IF 3.8 ) Pub Date : 2019-12-11 , DOI: 10.1016/j.jpdc.2019.11.011
Maurice Jamieson , Nick Brown

Micro-core architectures combine many low memory, low power computing cores together in a single package. These are attractive for use as accelerators but due to limited on-chip memory and multiple levels of memory hierarchy, the way in which programmers offload kernels needs to be carefully considered. In this paper we use Python as a vehicle for exploring the semantics and abstractions of higher level programming languages to support the offloading of computational kernels to these devices. By moving to a pass by reference model, along with leveraging memory kinds, we demonstrate the ability to easily and efficiently take advantage of multiple levels in the memory hierarchy, even ones that are not directly accessible to the micro-cores. Using a machine learning benchmark, we perform experiments on both Epiphany-III and MicroBlaze based micro-cores, demonstrating the ability to compute with data sets of arbitrarily large size. To provide context of our results, we explore the performance and power efficiency of these technologies, demonstrating that whilst these two micro-core technologies are competitive within their own embedded class of hardware, there is still a way to go to reach HPC class GPUs.



中文翻译:

高级编程抽象,可利用微核架构来利用分层存储器

微内核架构将许多低内存,低功耗计算内核整合到一个封装中。这些作为加速器是有吸引力的,但是由于片上内存有限以及内存层次结构的多个级别,需要仔细考虑程序员卸载内核的方式。在本文中,我们使用Python作为工具,探索高级编程语言的语义和抽象,以支持将计算内核卸载到这些设备。通过使用按引用传递模型以及利用各种内存,我们证明了能够轻松,有效地利用内存层次结构中多个级别的能力,甚至是微内核无法直接访问的级别。使用机器学习基准,我们在Epiphany-III和基于MicroBlaze的微核上都进行了实验,证明了使用任意大数据集进行计算的能力。为了提供我们的结果背景,我们探索了这些技术的性能和能效,证明了这两种微核技术在其自己的嵌入式硬件类别中具有竞争力,但仍然有一种达到HPC类GPU的方法。

更新日期:2020-01-04
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