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A 19.5% Efficiency 51–73-GHz High-Output Power Frequency Doubler in 65-nm CMOS
IEEE Microwave and Wireless Components Letters ( IF 2.374 ) Pub Date : 2019-11-28 , DOI: 10.1109/lmwc.2019.2949199
Zhilin Chen; Yiming Yu; Yunqiu Wu; Huihua Liu; Chenxi Zhao; Kai Kang

This letter presents a 51–73-GHz high-output power and efficiency frequency doubler, which is fabricated in a standard 65-nm CMOS process. The proposed frequency doubler adopts a fourth-order transformer-based balun and a dual- LC tank network to achieve wideband operating at input and output ports. In addition, a common-source amplifier with a Gm-boosting technique is used as an output buffer to improve the output power and efficiency. The measured results show that the doubler achieves input and output return losses below −10 dB from 26 to 36 GHz and 53 to 80 GHz, respectively. The measured maximum gain is 0.8 dB at 66 GHz with 22-GHz 3-dB gain bandwidth at an input power of 1 dBm. Furthermore, with an input power of 7 dBm, the proposed doubler also exhibits a high efficiency of 19.5% and an output power of 5.7 dBm at 66 GHz. The dc power consumption is 14 mW with 1-V power supply, and the chip size is $0.63\times0.52$ mm 2 including all test pads.
更新日期:2020-01-04

 

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