This letter presents a 51–73-GHz high-output power and efficiency frequency doubler, which is fabricated in a standard 65-nm CMOS process. The proposed frequency doubler adopts a fourth-order transformer-based balun and a dual-LC tank network to achieve wideband operating at input and output ports. In addition, a common-source amplifier with a Gm-boosting technique is used as an output buffer to improve the output power and efficiency. The measured results show that the doubler achieves input and output return losses below −10 dB from 26 to 36 GHz and 53 to 80 GHz, respectively. The measured maximum gain is 0.8 dB at 66 GHz with 22-GHz 3-dB gain bandwidth at an input power of 1 dBm. Furthermore, with an input power of 7 dBm, the proposed doubler also exhibits a high efficiency of 19.5% and an output power of 5.7 dBm at 66 GHz. The dc power consumption is 14 mW with 1-V power supply, and the chip size is $0.63\times0.52$ mm2 including all test pads.

中文翻译：

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65-nm CMOS 中效率为 19.5% 的 51-73-GHz 高输出功率倍频器

这封信展示了 51-73GHz 高输出功率和效率倍频器，它采用标准 65nm CMOS 工艺制造。所提出的倍频器采用基于四阶变压器的巴伦和双 LC 谐振网络来实现输入和输出端口的宽带操作。此外，采用 Gm 升压技术的共源放大器用作输出缓冲器，以提高输出功率和效率。测量结果表明，倍频器分别在 26 至 36 GHz 和 53 至 80 GHz 范围内实现了低于 -10 dB 的输入和输出回波损耗。测得的最大增益在 66 GHz 时为 0.8 dB，输入功率为 1 dBm 时具有 22-GHz 3-dB 增益带宽。此外，在输入功率为 7 dBm 的情况下，所提出的倍频器在 66 GHz 下也表现出 19.5% 的高效率和 5.7 dBm 的输出功率。