We present a new noise shaping method and a dual polarity calibration technique suited for successive approximation register type analog to digital converters (SAR-ADC). Noise is pushed to higher frequencies with the noise shaping by adding a switched capacitor. The SAR capacitor array mismatch has been compensated by the dual-polarity digital calibration with minimum circuit overhead. A proof-of-concept prototype SAR-ADC using the proposed techniques has been fabricated in a 0.5-μm standard CMOS technology. It achieves 67.7 dB SNDR at 62.5 kHz sampling frequency, while consuming 38.3μW power with 1.8 V supply.

中文翻译：

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具有双极性数字校准的 13 位噪声整形 SAR-ADC。

我们提出了一种新的噪声整形方法和一种适用于逐次逼近寄存器型模数转换器 (SAR-ADC) 的双极性校准技术。通过添加开关电容器进行噪声整形，将噪声推到更高的频率。SAR 电容器阵列失配已通过双极性数字校准以最小的电路开销得到补偿。使用所提出的技术的概念验证原型 SAR-ADC 已在 0.5-μm 标准 CMOS 技术中制造。它在 62.5 kHz 采样频率下实现 67.7 dB SNDR，同时在 1.8 V 电源下消耗 38.3μW 功率。