The paper addresses the passivation of Germanium surfaces by using layered La₂O₃/ZrO₂ high-k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed La_xGe_yO_z interfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (1 0 0) Ge down to 3 × 10¹¹ eV⁻¹ cm⁻² are demonstrated. The formation of the high-k La_xGe_yO_z layer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2 nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found.

该论文通过使用原子层沉积沉积的分层 La ₂ O ₃ /ZrO ₂高k电介质来钝化锗表面，以应用于基于 Ge 的 MOSFET 器件。证明了在存在薄 Pt 帽层的热后处理期间暴露于氧化和还原环境的这些多层栅极堆叠的改进的电性能。结果表明形成薄的混合 La _x Ge _y O _z厚度可通过氧化时间控制的界面层。通过 XPS、EDX/EELS 和 TEM 分析进一步研究了这种形成。额外的还原退火处理进一步改善了与 Ge 衬底接触的栅极电介质的电性能。结果证明了 (1 0 0) Ge 上低至 3 × 10 ¹¹  eV ^-1  cm ^{-2 的}低界面陷阱密度。高k La _x Ge _y O _{z 的形成}层与氧化物致密化理论一致，可以解释界面陷阱密度的提高。讨论了在基于 Ge 的基于 MOS 的器件结构中使用的各个分层栅极电介质对 1.2 nm 或以下的 EOT 的缩放潜力。发现了改进的界面陷阱密度和降低的等效氧化物厚度之间的折衷。