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A VLSI design of a pipeline Reed-Solomon decoder.
IEEE Transactions on Computers ( IF 3.7 ) Pub Date : 1985-05-01
H M Shao 1 , T K Truong , L J Deutsch , J H Yuen , I S Reed
Affiliation  

A pipeline structure of a transform decoder similar to a systolic array is developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error-locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new coder is regular and simple, and naturally suitable for VLSI implementation. An example illustrating both the pipeline and systolic array aspects of this decoder structure is given for a RS code.

中文翻译:

管道Reed-Solomon解码器的VLSI设计。

开发了类似于心跳阵列的变换解码器的流水线结构来解码里德-所罗门(RS)码。该设计的重要组成部分是用于计算错误定位器多项式的改进的欧几里得算法。在Euclid算法的这种修改中,完全避免了逆场元素的计算。新的编码器是常规且简单的,自然适用于VLSI实现。对于RS码,给出了说明该解码器结构的流水线和脉动阵列方面的示例。
更新日期:2019-11-01
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